EDN

‘Wrap’ your cores to enable SoC test

Deep submicron technology enabled the design of the industry's first very large chips. The magnitude of the design effort involved in creating these chips led to the adoption of reuse methodologies ...
EDN

3-D bin packing algorithm proposed for SoC testing

Researchers from Mentor Graphics Corp. are proposing a more complete way to test multiple cores on a system-on-chip. At the International Test Conference, Mentor presented a paper that defines SoC ...
Electronic Design

Synopsys Debuts DesignWare STAR Hierarchical System to Accelerate SoC Test

September 11, 2013. Synopsys Inc. has announced the availability of its DesignWare STAR Hierarchical System, an automated hierarchical test solution for efficiently testing SoCs, including ...
Electronic Design

SoC Test System Speeds Design Verification, Cuts Test Cost

As System-On-A-Chip complexity increases, testing the millions of gates that get integrated on the chip has become an ever more challenging and more expensive task. On-chip test support logic and ...
Semiconductor Engineering

System-Level Testing – The New Paradigm for Semiconductor Quality Control

Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span ...